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<h1>A Synchronous Register to Store and Control Data</h1>
<p>It may seem silly to implement a register module rather than let the HDL
 infer it, but doing so separates data and control at the most basic level,
 including various kinds of resets, which are part of control. This
 separation of data and control allows us to simplify the control logic and
 reduce the need for some routing resources.</p>
<h2>Power-on-Reset</h2>
<p>On FPGAs, the initial state of registers is set in the configuration
 bitstream and applied by special power-on reset circuitry. The initial
 state of a design is available "for free" <em>and can be returned to at
 run-time</em>, which removes the need for that control and data logic.</p>
<h2>Asynchronous Reset</h2>
<p>The asynchronous reset is not implemented here as its existence prevents
 register retiming, even if tied to zero. This limitation complicates design
 and reduces performance as we would have to manually place registers to
 properly pipeline logic. If you absolutely need an asynchronous reset for
 ASIC implementation or for some critical registers, use the
 <a href="./Register_areset.html">Register_areset</a> instead.</p>
<h2>Synchronous Reset (a.k.a. Clear)</h2>
<p>If you need to clear the register during normal operation, use the
 synchronous clear input. This may create extra logic, but that logic gets
 folded into other logic feeding data to the register, and would have been
 necessary anyway but present as another case in the surrounding logic.
 Having a clear input allows us to get to the initial power-on-reset state
 without complicating the design.</p>
<h2>Implementation</h2>
<p>Let's begin with the usual front matter:</p>

<pre>
`default_nettype none

module <a href="./Register.html">Register</a>
#(
    parameter WORD_WIDTH  = 0,
    parameter RESET_VALUE = 0
)
(
    input   wire                        clock,
    input   wire                        clock_enable,
    input   wire                        clear,
    input   wire    [WORD_WIDTH-1:0]    data_in,
    output  reg     [WORD_WIDTH-1:0]    data_out
);

    initial begin
        data_out = RESET_VALUE;
    end
</pre>

<p>Here, we use the  "last assignment wins" idiom (See
 <a href="./verilog.html#resets">Resets</a>) to implement reset.  This is also one
 place where we cannot use ternary operators, else the last assignment for
 clear (e.g.: <code>data_out &lt;= (clear == 1'b1) ? RESET_VALUE : data_out;</code>) would
 override any previous assignment with the current value of <code>data_out</code> if
 <code>clear</code> is not asserted!</p>

<pre>
    always @(posedge clock) begin
        if (clock_enable == 1'b1) begin
            data_out <= data_in;
        end

        if (clear == 1'b1) begin
            data_out <= RESET_VALUE;
        end
    end

endmodule
</pre>

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